1. Field of the Invention
The present invention relates to a digital data recording and reproducing apparatus which records and reproduces digital data, and more particularly to a digital data dividing apparatus which is used in the digital data recording and reproducing apparatus.
2. Description of Related Art
As home color television sets with larger screens have become popular in recent years, a number of improvements in video signal recording and reproduction media have been made to obtain higher picture quality. In the meantime, vigorous efforts to develop magnetic recording and reproduction apparatuses of digital information (digital VTR hereafter) for home use which digitize video signals and record them through bandwidth compression (high-efficiency encoding) and reproduce them have been made by manufacturers, as the data storage media for recording and reproducing high-quality video data while retaining the high picture quality.
The method of recording and reproduction with a conventional home digital VTR will be described below, taking an example in the recording and reproduction process of Phillips Corp., which is reported in "An experimental digital VCR with 40 mm drum, single actuator and DCT-based bit-rate reduction," PP. 597-605, IEEE Transactions in Consumer Electronics, Vol. 34, No. 3 (August, 1988).
FIG. 1 shows a block diagram of the recording system of a prior art home digital VCR. It is assumed that this system employs 2-channel recording system. In FIG. 1, elements 1a through 1c are input terminals, elements 2a through 2c are A/D converters which convert analog data to digital data, numeral 3 denotes a high-efficiency encoder which applies high-efficiency encoding to a luminance signal Y and color signals CB and CR which have been fed as inputs, numeral 4 denotes an error correction encoder which adds error-correcting code to 2-channel output data from the high-efficiency encoder 3 in order to correct or detect errors which take place during reproduction, numerals 5a, 5b denote digital modulator circuits which apply digital modulation to the output data from the error correction encoder 4, numerals 6a, 6b denote sync-signal adding circuits which add sync signals and ID signals, numerals 7a, 7b denote recording amplifiers, numerals 8a, 8b denote rotary heads, and numeral 9 denote a magnetic tape.
FIG. 2 shows a block diagram of the reproduction system of a prior art home digital VCR. In FIG. 2, numerals 8a, 8b and 9 denote the same as in FIG. 1 and description thereof will be omitted. Numerals 10a, 10b denote head amplifiers which amplify the signals reproduced by the rotary heads 8a, 8b, numerals 11a, 11b denote data detectors which detect data from the reproduced signals as well as detect and correct jitter in the reproduced signals, numerals 12a, 12b denote digital demodulators, numeral 13 denotes an error correction decoder which detects and corrects errors in the reproduced signals, numeral 14 denotes a high-efficiency decoder which applies high-efficiency decoding to the output of the error correction decoder 13 to restore video signals, numerals 15a through 15c denote D/A converters which convert digital signals to analog signals, and numerals 16a through 16c denote output terminals.
FIG. 3 shows a block diagram of a prior art high-efficiency encoder 3 described in the above-mentioned literature. In FIG. 3, numerals 17a, 17b denote field memories, numeral 18 denotes a DCT circuit which applies discrete cosine transform (DCT hereafter) to each block of output data of the field memories 17a, 17b which has been structured into specified blocks of the field memories 17a, 17b, numeral 19 denotes an adaptive quantizer which quantizes the coefficients which have been transformed by the DCT circuit 18, numeral 20 denotes a variable-length encoder which applies variable-length encoding to the output from the adaptive quantizer 19, numeral 21 denotes a buffer memory used to provide the output of the variable-length encoder 20 at a fixed rate and numeral 22 denotes a buffer controller which switches the quantization parameter of the adaptive quantizer 19 and selects the components to be encoded in the variable-length encoder 20. The field memories 17a, 17b, the DCT circuit 18, the adaptive quantizer 19, the variable-length encoder 20, the buffer memory 21 and the buffer controller 22 constitute the high-efficiency encoder 3.
FIG. 4 shows a block diagram of a prior art high-efficiency decoder 14. In FIG. 4, numeral 23 denotes a variable-length decoder which converts the variable-length encoded data to the original fixed-length data, numeral 25 denotes an inverse adaptive quantizer, numeral 26 denotes an inverse DCT circuit which applies inverse discrete cosine transform (called inverse DCT hereafter) to the output data of the inverse adaptive quantizer 25 and numerals 27a, 27b denote field memories used to apply a specified delay to the reproduced digital signal output from the inverse DCT circuit 26 and give an output by decoding the data which was structured into blocks during recording. The variable-length decoder 23, the buffer memory 24, the inverse adaptive quantizer 25, the inverse DCT circuit 26, and the field memories 27a, 27b constitute the high-efficiency decoder 14.
The operation of the recording system will now be described below with reference to FIG. 1. The luminance signal Y and the two color signals CB and CR which have been supplied via the input terminals 1a through 1c are converted from analog to digital signals by the A/D converters 2a through 2c, and the recording bit rate thereof is reduced by the high-efficiency encoder 3. Operation of the high-efficiency encoder 3 will be described in detail below. The data with the recording bit rate having been reduced by the high-efficiency encoder 3 is provided with an error-correcting code which is generated to detect and correct errors which take place during reproduction. The recording digital signals with the error-correcting code (called check hereinafter) added thereto in the error correction encoder 4 are processed in the digital demodulators 5a, 5b in the specified modulation rule to suppress the low-frequency components of the recording signal (digital modulation). The recording signals which have been digital-modulated are provided with sync-signal, ID signal and the like added thereto in the sync-signal adding circuits 6a, 6b and, after being amplified by the recording amplifiers 7a, 7b, recorded on the magnetic tape 9 via the rotary heads 8a, 8b.
Operation of the reproduction system will now be described similarly with reference to FIG. 2. The 2-channel reproduction signals which were reproduced from the magnetic tape 9 via the rotary heads 8a, 8b are amplified by the head amplifiers 10a and 10b , then converted into digital data by the data detectors 11a, 11b while the jitter (time domain error) included in the reproduced signals is absorbed. Then digital demodulation is applied to the signals by the digital demodulators 12a, 12b to convert them to reproduced digital signals, which are supplied to the error correction decoder 13, The error correction decoder 13, based on the check added during recording, detects or corrects errors which occur in the reproduction signals. The reproduction signals, with errors detected and corrected by the error correction decoder 13, are subjected to variable-length decoding and inverse DCT by the high-efficiency decoder 14, then restored to the original luminance signal and the two color signals CB, CR, which are converted to analog signals by the D/A converters 15a through 15c and are applied to the output terminals 16a through 16c as output signals.
The operation of the high-efficiency encoder 3 will now be described below with reference to FIG. 3. The input luminance signal Y and two color signals CB and CR are processed in the field memories 17a, 17b to be delayed by a specified time period and structured into blocks each including eight lines of eight pixels each. The luminance signal Y and the two color signals CB and CR which have been structured into blocks are subjected to time-division multiplexing and supplied to the DCT circuit 18. The outputs of the field memories 17a, 17b in the form of blocks are subjected to DCT processing in the DCT circuit 18. That is, denoting the data of each pixel in a block as X (i,j) (i=0, 1, . . . , 7; j=0, 1, . . . , 7), the DCT circuit 18 first calculates the DCT of eight points in horizontal direction, namely calculates the following expressions ##EQU1## (where m=1, . . . , 7; j=0, 1, . . . ,7).
Then DCT of eight points in vertical direction is performed for the converted data f(m, j) (where m=0, . . . , 7; j=0,1, . . . , 7) to calculate the following. ##EQU2## (where n=1, . . . , 7; m=0,1, . . . , 7).
Then these conversion coefficients F(m,n) (m=0, . . . , 7); n=0,1, . . . , 7) are given as output. Conversion coefficients F(m,n) thus obtained with small values of m and n determine the basic picture quality and represent low-frequency components which include DC, and those of greater values of m and n represent components of higher frequencies and give the fine picture information.
Conversion coefficients supplied from the DCT circuit 18 are quantized by the adaptive quantizer 19, which holds a plurality of quantization tables of different quantization steps, and switches the quantization steps based on the conversion coefficient of each block and parameters obtained from the buffer memory 21. For example, rise-up portions of high contrast are roughly quantized and details of less amplitudes are finely quantized. Output of the adaptive quantizer 19 is subjected to variable-length coding in the variable-length encoder 20, and is fed to the buffer memory 21, from which it is later read at a fixed rate. The buffer controller 22 detects data stored in the buffer memory 21 and determines the quantization parameter based on the amount of data to control the adaptive quantizer 19. The buffer controller 22 also uses the amount of data stored in the buffer memory 21 to determine the conversion coefficients of encoding in the variable-length encoder 20.
The operation of the high-efficiency decoder 14 will now be described below with reference to FIG. 4. The reproduction digital signals supplied from the error correction decoder 13 are subjected to variable-length decoding in the variable-length decoder 23 and converted to fixed-length data. In the buffer memory 24, fixed-length data which has been subjected to variable-length decoding is read at a fixed rate. The fixed-length data which has been read from the buffer memory 24 is inverse-quantized by the inverse adaptive quantizer 25 and supplied to the inverse DCT circuit 26 which applies inverse DCT to the reproduction digital signals. The reproduced luminance signal Y and the two reproduced color signals CB and CR which have been subject to inverse DCT are temporarily stored in the field memories 27a, 27b and are provided with a specified amount of delay, and then supplied to D/A converts 15a through 15c with the block structure which was applied during recording being decoded.
FIG. 5 shows the pattern of the recording tracks formed on the magnetic tape 9 of digital VTR which employs 2-channel recording system of the prior art. In this example, it is assumed that data of two channels are recorded simultaneously on the magnetic tape 9 as shown in FIG. 5. A and B in the figure represent the recording tracks formed by the rotary heads of different channels. The rotary heads of the respective channel are assumed to have different azimuth angles.
The prior art digital VTR has been described above. When editing video data with a digital VTR having such a recording format, problems of servo control, unsteadiness of the track, etc. which are characteristic to VTR sometimes cause overwrite of the track of another channel which has been recorded, thereby destroying the data on the track of the other channel. As a result, about half of the video data in one field is not reproduced making it difficult to obtain good video images when the data is reproduced with the track on one channel being over-written.
As a means to obtain reproduced images of acceptable quality even when the data on one track is completely destroyed, there is a method of using an interleave format represented by the digital audio tape recorder. In a digital audio tape recorder, data of even-numbered samples is recorded on the track of one channel and data of odd-numbered samples is recorded on the track of another channel. With this method, even when the information of the track of channel A is not reproduced (data is destroyed by over-writing), the information which would have been recorded on channel A is restored through the use of interpolation by using the information on the track of channel B.
In the case of prior art digital VTR discussed above, however, because bandwidth compression (high-efficiency encoding) is applied by means of DCT transform or variable-length encoding, when the conversion coefficients described above are divided into two channels alternately, it is difficult to determine all conversion coefficients by interpolation if the data of one channel cannot be reproduced, resulting in a problem that a satisfactorily reproduced image cannot be obtained at splicing points of editing.
There has also been a problem that writing every piece of data on each track twice leads to an increase in the redundancy of recording data.